DESIGN AND FPGA IMPLEMENTATION OF AN EFFICIENT PARALLEL TURBO DECODER FOR COMBINING STATE METRIC CALCULATIONS

Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations

In order to achieve the requirement of high throughput and low-power in wireless communication, a parallel Turbo decoder has attracted extensive attention.By analyzing the calculating of CHROMIUM the state metrics, a low-resource parallel Turbo decoder architecture scheme based on merging the forward and backward state metrics calculation modules w

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